The Next Generation of Compiler Technology

by Dave McAllister and Michael Stebbins

With the release of new Silicon Graphics^® platforms based on the MIPS^® R5000^TM and R10000^TM, new compiler technology is necessary to take full advantage of the capabilities of the new hardware. With this in mind, MIPSáTechnologies and Silicon Graphics have completed work on a new set of compiler products, based on the premise of quality support for new architectures and the new N32 application binary interface (ABI).

Over the past few years, MIPS has introduced several new instruction set architectures (ISAs), from MIPSáI to MIPSáIV. To take advantage of new CPU designs, successive ISAs added functionality, which is summarized as follows:

MIPS I: Provided the base instruction set, with a load-delay slot required.

MIPS II: Eliminated load-slot requirement; added coprocessor (FPU) 64-bit loads and stores, ll/sc (load linked, store conditional), MP synchronization primitives, sync instruction, branch likely instructions, trap on condition, and square root instruction.

MIPS III: Widened integer registers to 64-bits; added load and store of 64-bit register instructions, integer arithmetic and logical operations on 64-bit registers, int-FPU moves; added 16 64-bit FP registers for a total of 32 64-bit FP registers.

MIPS IV: Added conditional moves, floating-point multiply/add, floating-point indexed addressing mode, prefetch instructions, multiple floating-point condition codes, imprecise exceptions, and a reciprocal square root instruction.

The original ABI design was based on the MIPSáI ISA, and has limitations that may prevent applications from taking full advantage of new CPU capabilities.

Enter the 64-bit Data Model

With the introduction of systems that supported the MIPSáIII/IV ISA, the original compiler model was found to be lacking, as was the 32-bit data model itself. MIPS produced an ABI based on a 64-bit data model, which was supported on IRIX^TMá6.0, IRIXá6.0.1, and IRIXá6.1. The MIPSpro^TMáVersioná6.0 compilers were the first to support this new data model.

Taking Advantage of 64-bit Architectures without the Porting Hassles

Many of you may remember porting 16-bit programs to 32-bit CPUs in the early days of 32-bit RISC^TM processors. Assumptions made on the natural size of integers and pointers caused porting headaches. The same holds true for porting code written for 32- to 64-bit architectures. Many assumptions are based on the natural size of an integer (32 bits) and the natural size of a pointer (32 bits). As we developed experience with the 64-bit model, and the migration from the 32-bit application world, we required a new ABI that provided a clean migration path for 32-bit applications, but that retained support for new CPU features and the later ISAs. The N32 ABI was established to provide the best crossover in features and portability from the old ISA to the new.

With N32 you have access to all of the instructions and registers of the 64-bit ABI. The ABI name convention refers to the size of the address space--32-bit addresses versus 64-bit addresses. The numbering in the naming convention does not indicate the ability to use or not use 64-bit operations in binaries. In reality, N32 supports 64-bit integer and floating point operations with single instructions. However, N32 supports only 32-bit address spaces with 32-bit pointers. The following table illustrates how you can make efficient use of the architecture while porting 32-bit code.

**Table: ABI Comparison Summary**
	o32	N32	N64
Compiler	IRIX ucode	MIPSpro	MIPSpro
Integer model	ILP32	ILP32	LP64
Calling convention	MIPS	new	new
Number of FP registers (double precision)	16	32	32
Number of argument registers	4	8	8
Debug symbol table format	mdebug	dwarf	dwarf
ISA supported	MIPS I/II	MIPS III/IV	MIPS III/IV
32/64 mode	32-bit registers and addresses	64-bit registers; 32-bit addresses	64-bit registers and addresses

To gain advantage from N32, do the following:

Run an IRIXá6.2-based system.
Change Makefiles to use the -n32 compiler option.
Rework Assembly code to conform to N32 calling sequences.
Recompile all code with the MIPSproáVersioná7.0 compiler that supports N32.

The N32 environment is available with IRIXá6.2 for systems based on the following CPU families: R4000^® (Version 2.2 or higher), R4400^®, R4600^TM, R5000^TM, R8000^®, R10000^TM and future products. For the best performance on R5000, R8000, and R10000 systems, you need to use -mips4; for optimal performance on R4x00-based systems, you need to use -mips3.

New Compilers

While continuing to support the o32 (ucode) model, Silicon Graphics now offers new technology that optimizes your application's use of current as well as future CPU architectures. This suite of high-performance compilers will push the barriers of optimization technology, while providing full language support (ANSI standards plus multi-vendor extensions), multi-processing features and fast compilation.

The primary features of this generation of compilers include

Higher compilation performance for 64 and N32 development
High run-time performance
Source code compatible with current compilers

In addition to existing compiler technologies such as software pipelining (using every machine cycle in a loop), traditional optimizers, and improved code generators, the next generation of compilers provides new technology, consisting of several new components, such as an Inter-Procedural Analyzer and a Loop Nest Optimizer.

With the release of the MIPSproáVersioná7.0 compilers, you have a choice of two technologies: IRIX ucode compiler and MIPSproáVersioná7.0. Each has specific advantages and targets certain CPU architectures, which are described briefly here:

IRIX ucode compiler
Generates code for MIPSá1 and MIPS2 that runs on all Silicon Graphics systems. The generated code is upward compatible, but uses only a small portion of the full power of the new architectures. This option supports the o32 ABI only.
MIPSproáVersioná7.0
Generates code for systems based on R10000, R8000, R5000, and R4x00 processors. For the first release, the code is tuned primarily for R10000 and R5000 systems. You need IRIXá6.2 in order to run this code (-n32 or -64). As with the MIPSproáVersioná6.0 compiler family, the -o32 flag invokes the ucode compilers to produce -o32 MIPSáI/II code. You can also use either the -r8000 or the -TARG:platform=ip26 (or ip21) option to generate R8000 code.

Summary

With the introduction of the N32 ABI, Silicon Graphics and MIPSáTechnology provide a clean migration path from older 32-bit based application development to products designed to provide the utmost performance on the new system technology. By providing a new environment to allow you to continue the same development environment as the older products, Silicon Graphics has worked to protect your current investment in your application development without requiring you to re-engineer your code. And with the advances in CPU technology provided by the R5000 and R10000, N32 will deliver even more performance to make your applications that much faster.

We welcome feedback and comments at devprogram@sgi.com.